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MC6809-MC6809E 8-Bit Microprocessor Programming Manual [M6809PM/AD]
© Motorola Inc., 1981

APPENDIX A - INSTRUCTION SET DETAILS

A.1 INTRODUCTION

This appendix contains detailed information about each instruction in the MC6809 instruction set. They are arranged in an alphabetical order with the mnemonic heading set in larger type for easy reference.

A.2 NOTATION

In the operation description for each instruction, symbols are used to indicate the operation. Table A-1 lists these symbols and their meanings. Abbreviations for the various registers, bits, and bytes are also used. Table A-2 lists these abbreviations and their meanings.

Table A-1. Operation Notation
SymbolMeaning
Is transferred to
Boolean AND
Boolean OR
Boolean exclusive OR
‾‾ (Overline)Boolean NOT
:Concatenation
+Arithmetic plus
-Arithmetic minus
×Arithmetic multiply
Table A-2. Register Notation
AbbreviationMeaning
ACCA or AAccumulator A
ACCB or BAccumulator B
ACCA:ACCB or DDouble accumulator D
ACCXEither accumulator A or B
CCR or CCCondition code register
DPR or DPDirect page register
EAEffective address
IFFIf and only if
IX or XIndex register X
IY or YIndex register Y
LSNLeast significant nibble
MMemory location
MIMemory immediate
MSNMost significant nibble
PCProgram counter
RA register before the operation
R'A register after the operation
TEMPTemporary storage location
xxHMost significant byte of any 16-bit register
xxLLeast significant byte of any 16-bit register
Sp or SHardware Stack pointer
Us or UUser Stack pointer
PA memory argument with Immediate, Direct, Extended, and Indexed addressing modes
QA read-modify-write argument with Direct, Indexed, and Extended addressing modes
( )The data pointed to by the enclosed (16-bit address)
dd8-bit branch offset
DDDD16-bit branch offset
#Immediate value follows
$Hexadecimal value follows
[ ]Indirection
'Indicates indexed addressing
ABXAdd Accumulator B into Index Register XABX
Source Form:ABX
Operation:IX' ← IX + ACCB
Condition Codes:Not affected.
Description:Add the 8-bit unsigned value in accumulator B into index register X.
Addressing Mode:Inherent
ADCAdd with Carry into RegisterADC
Source Forms:ADCA P; ADCB P
Operation:R' ← R + M + C
Condition Codes:
H-Set if a half-carry is generated; cleared otherwise.
N-Set if the result is negative; cleared otherwise.
Z-Set if the result is zero; cleared otherwise.
V-Set if an overflow is generated; cleared otherwise.
C-Set if a carry is generated; cleared otherwise.
Description:Adds the contents of the C (carry) bit and the memory byte into an 8-bit accumulator.
Addressing Modes:Immediate
Extended
Direct
Indexed
ADD (8-Bit)Add Memory into RegisterADD (8-Bit)
Source Forms:ADDA P; ADDB P
Operation:R' ← R + M
Condition Codes:
H-Set if a half-carry is generated; cleared otherwise.
N-Set if the result is negative; cleared otherwise.
Z-Set if the result is zero; cleared otherwise.
V-Set if an overflow is generated; cleared otherwise.
C-Set if a carry is generated; cleared otherwise.
Description:Adds the memory byte into an 8-bit accumulator.
Addressing Modes:Immediate
Extended
Direct
Indexed
ADD (16-Bit)Add Memory into RegisterADD (16-Bit)
Source Forms:ADDD P
Operation:R' ← R + M:M+1
Condition Codes:
H-Not affected.
N-Set if the result is negative; cleared otherwise.
Z-Set if the result is zero; cleared otherwise.
V-Set if an overflow is generated; cleared otherwise.
C-Set if a carry is generated; cleared otherwise.
Description:Adds the 16-bit memory value into the 16-bit accumulator
Addressing Modes:Immediate
Extended
Direct
Indexed
ANDLogical AND Memory into RegisterAND
Source Forms:ANDA P; ANDB P
Operation:R' ← R ∧ M
Condition Codes:
H-Not affected.
N-Set if the result is negative; cleared otherwise.
Z-Set if the result is zero; cleared otherwise.
V-Always cleared.
C-Not affected.
Description:Performs the logical AND operation between the contents of an accumulator and the contents of memory location M and the result is stored in the accumulator.
Addressing Modes:Immediate
Extended
Direct
Indexed
ANDLogical AND Immediate Memory into Condition Code RegisterAND
Source Form:ANDCC #xx
Operation:R' ← R ∧ MI
Condition Codes:Affected according to the operation.
Description:Performs a logical AND between the condition code register and the immediate byte specified in the instruction and places the result in the condition code register.
Addressing Mode:Immediate
ASLArithmetic Shift LeftASL
Source Forms:ASL Q; ASLA; ASLB
Operation:
C           0
b7b0
Condition Codes:
H-Undefined.
N-Set if the result is negative; cleared otherwise.
Z-Set if the result is zero; cleared otherwise.
V-Loaded with the result of the exclusive OR of bits six and seven of the original operand.
C-Loaded with bit seven of the original operand.
Description:Shifts all bits of the operand one place to the left. Bit zero is loaded with a zero. Bit seven is shifted into the C (carry) bit.
Addressing Modes:Inherent
Extended
Direct
Indexed
ASRArithmetic Shift RightASR
Source Forms:ASR Q; ASRA; ASRB
Operation:
b7           C
b7b0
Condition Codes:
H-Undefined.
N-Set if the result is negative; cleared otherwise.
Z-Set if the result is zero; cleared otherwise.
V-Not affected.
C-Loaded with bit zero of the original operand.
Description:Shifts all bits of the operand one place to the right. Bit seven is held constant. Bit zero is shifted into the C (carry) bit.
Addressing Modes:Inherent
Extended
Direct
Indexed
BCCBranch on Carry ClearBCC
Source Forms:BCC dd; LBCC DDDD
Operation:TEMP ← MI
IFF C = 0 then PC' ← PC + TEMP
Condition Codes:Not affected.
Description:Tests the state of the C (carry) bit and causes a branch if it is clear.
Addressing Mode:Relative
Comments:Equivalent to BHS dd; LBHS DDDD
BCSBranch on Carry SetBCS
Source Forms:BCS dd; LBCS DDDD
Operation:TEMP ← MI
IFF C = 1 then PC' ← PC + TEMP
Condition Codes:Not affected.
Description:Tests the state of the C (carry) bit and causes a branch if it is set.
Addressing Mode:Relative
Comments:Equivalent to BLO dd; LBLO DDDD
BEQBranch on EqualBEQ
Source Forms:BEQ dd; LBEQ DDDD
Operation:TEMP ← MI
IFF Z = 1 then PC' ← PC + TEMP
Condition Codes:Not affected.
Description:Tests the state of the Z (zero) bit and causes a branch if it is set. When used after a subtract or compare operation, this instruction will branch if the compared values, signed or unsigned, were exactly the same.
Addressing Mode:Relative
BGEBranch on Greater than or Equal to ZeroBGE
Source Forms:BGE dd; LBGE DDDD
Operation:TEMP ← MI
IFF [N ⊕ V] = 0 then PC' ← PC + TEMP
Condition Codes:Not affected.
Description:Causes a branch if the N (negative) bit and the V (overflow) bit are either both set or both clear. That is, branch if the sign of a valid twos complement result is, or would be, positive. When used after a subtract or compare operation on twos complement values, this instruction will branch if the register was greater than or equal to the memory operand.
Addressing Mode:Relative
BGTBranch on GreaterBGT
Source Forms:BGT dd; LBGT DDDD
Operation:TEMP ← MI
IFF Z ∧ [N ⊕ V] = 0 then PC' ← PC + TEMP
Condition Codes:Not affected.
Description:Causes a branch if the N (negative) bit and V (overflow) bit are either both set or both clear and the Z (zero) bit is clear. In other words, branch if the sign of a valid twos complement result is, or would be, positive and not zero. When used after a subtract or compare operation on twos complement values, this instruction will branch if the register was greater than the memory operand.
Addressing Mode:Relative
BHIBranch if HigherBHI
Source Forms:BHI dd; LBHI DDDD
Operation:TEMP ← MI
IFF [ C ∨ Z ] = 0 then PC' ← PC + TEMP
Condition Codes:Not affected.
Description:Causes a branch if the previous operation caused neither a carry nor a zero result. When used after a subtract or compare operation on unsigned binary values, this instruction will branch if the register was higher than the memory operand.
Addressing Mode:Relative
Comments:Generally not useful after INC/DEC, LD/TST, and TST/CLR/COM instructions.
BHSBranch if Higher or SameBHS
Source Forms:BHS dd; LBHS DDDD
Operation:TEMP ← MI
IFF C = 0 then PC' ← PC + MI
Condition Codes:Not affected.
Description:Tests the state of the C (carry) bit and causes a branch if it is clear. When used after a subtract or compare on unsigned binary values, this instruction will branch if the register was higher than or the same as the memory operand.
Addressing Mode:Relative
Comments:This is a duplicate assembly-language mnemonic for the single machine instruction BCC. Generally not useful after INC/DEC, LD/ST, and TST/CLR/COM instructions.
BITBit TestBIT
Source Form:Bit P
Operation:TEMP ← R ∧ M
Condition Codes:
H-Not affected.
N-Set if the result is negative; cleared otherwise.
Z-Set if the result is zero; cleared otherwise.
V-Always cleared.
C-Not affected.
Description:Performs the logical AND of the contents of accumulator A or B and the contents of memory location M and modifies the condition codes accordingly. The contents of accumulator A or B and memory location M are not affected.
Addressing Modes:Immediate
Extended
Direct
Indexed
BLEBranch on Less than or Equal to ZeroBLE
Source Forms:BLE dd; LBLE DDDD
Operation:TEMP ← MI
IFF Z ∨ [ N ⊕ V ] = 1 then PC' ← PC + TEMP
Condition Codes:Not affected.
Description:Causes a branch if the exclusive OR of the N (negative) and V (overflow) bits is 1 or if the Z (zero) bit is set. That is, branch if the sign of a valid twos complement result is, or would be, negative. When used after a subtract or compare operation on twos complement values, this instruction will branch if the register was less than or equal to the memory operand.
Addressing Mode:Relative
BLOBranch on LowerBLO
Source Forms:BLO dd; LBLO DDDD
Operation:TEMP ← MI
IFF C = 1 then PC' ← PC + TEMP
Condition Codes:Not affected.
Description:Tests the state of the C (carry) bit and causes a branch if it is set. When used after a subtract or compare on unsigned binary values, this instruction will branch if the register was lower than the memory operand.
Addressing Mode:Relative
Comments:This is a duplicate assembly-language mnemonic for the single machine instruction BCS. Generally not useful after INC/DEC, LD/ST, and TST/CLR/COM instructions.
BLSBranch on Lower or SameBLS
Source Forms:BLS dd; LBLS DDDD
Operation:TEMP ← MI
IFF (C ∨ Z) = 1 then PC' ← PC + TEMP
Condition Codes:Not affected.
Description:Causes a branch if the previous operation caused either a carry or a zero result. When used after a subtract or compare operation on unsigned binary values, this instruction will branch if the register was lower than or the same as the memory operand.
Addressing Mode:Relative
Comments:Generally not useful after INC/DEC, LD/ST, and TST/CLR/COM instructions.
BLTBranch on Less than ZeroBLT
Source Forms:BLT dd; LBLT DDDD
Operation:TEMP ← MI
IFF [ N ⊕ V ] = 1 then PC' ← PC + TEMP
Condition Codes:Not affected.
Description:Causes a branch if either, but not both, of the N (negative) or V (overflow) bits is set. That is, branch if the sign of a valid twos complement result is, or would be, negative. When used after a subtract or compare operation on twos complement binary values, this instruction will branch if the register was less than the memory operand.
Addressing Mode:Relative
BMIBranch on MinusBMI
Source Forms:BMI dd; LBMI DDDD
Operation:TEMP ← MI
IFF N = 1 then PC' ← PC + TEMP
Condition Codes:Not affected.
Description:Tests the state of the N (negative) bit and causes a branch if set. That is, branch if the sign of the twos complement result is negative.
Addressing Mode:Relative
Comments:When used after an operation on signed binary values, this instruction will branch if the result is minus. It is generally preferred to use the LBLT instruction after signed operations.
BNEBranch Not EqualBNE
Source Forms:BNE dd; LBNE DDDD
Operation:TEMP ← MI
IFF Z = 0 then PC' ← PC + TEMP
Condition Codes:Not affected.
Description:Tests the state of the Z (zero) bit and causes a branch if it is clear. When used after a subtract or compare operation on any binary values, this instruction will branch if the register is, or would be, not equal to the memory operand.
Addressing Mode:Relative
BPLBranch on PlusBPL
Source Forms:BPL dd; LBPL DDDD
Operation:TEMP ← MI
IFF N = 0 then PC' ← PC + TEMP
Condition Codes:Not affected.
Description:Tests the state of the N (negative) bit and causes a branch if it is clear. That is, branch if the sign of the twos complement result is positive.
Addressing Mode:Relative
Comments:When used after an operation on signed binary values, this instruction will branch if the result (possibly invalid) is positive. It is generally preferred to use the BGE instruction after signed operations.
BRABranch AlwaysBRA
Source Forms:BRA dd; LBRA DDDD
Operation:TEMP ← MI
PC' ← PC + TEMP
Condition Codes:Not affected.
Description:Causes an unconditional branch.
Addressing Mode:Relative
BRNBranch NeverBRN
Source Forms:BRN dd; LBRN DDDD
Operation:TEMP ← MI
Condition Codes:Not affected.
Description:Does not cause a branch. This instruction is essentially a no operation, but has a bit pattern logically related to branch always.
Addressing Mode:Relative
BSRBranch to SubroutineBSR
Source Forms:BSR dd; LBSR DDDD
Operation:TEMP ← MI
SP' ← SP-1, (SP) ← PCL
SP' ← SP-1, (SP) ← PCH
PC' ← PC + TEMP
Condition Codes:Not affected.
Description:The program counter is pushed onto the stack. The program counter is then loaded with the sum of the program counter and the offset.
Addressing Mode:Relative
Comments:A return from subroutine (RTS) instruction is used to reverse this process and must be the last instruction executed in a subroutine.
BVCBranch on Overflow ClearBVC
Source Forms:BVC dd; LBVC DDDD
Operation:TEMP ← MI
IFF V = 0 then PC' ← PC + TEMP
Condition Codes:Not affected.
Description:Tests the state of the V (overflow) bit and causes a branch if it is clear. That is, branch if the twos complement result was valid. When used after an operation on twos complement binary values, this instruction will branch if there was no overflow.
Addressing Mode:Relative
BVSBranch on Overflow SetBVS
Source Forms:BVS dd; LBVS DDDD
Operation:TEMP' ← MI
IFF V = 1 then PC' ← PC + TEMP
Condition Codes:Not affected.
Description:Tests the state of the V (overflow) bit and causes a branch if it is set. That is, branch if the twos complement result was invalid. When used after an operation on twos complement binary values, this instruction will branch if there was an overflow.
Addressing Mode:Relative
CLRClearCLR
Source Form:CLR Q
Operation:TEMP ← M
M ← 0016
Condition Codes:
H-Not affected.
N-Always cleared.
Z-Always set.
V-Always cleared.
C-Always cleared.
Description:Accumulator A or B or memory location M is loaded with 000000002. Note that the EA is read during this operation.
Addressing Modes:Inherent
Extended
Direct
Indexed
CMP (8-Bit)Compare Memory from RegisterCMP (8-Bit)
Source Forms:CMPA P; CMPB P
Operation:TEMP ← R - M
Condition Codes:
H-Undefined.
N-Set if the result is negative; cleared otherwise.
Z-Set if the result is zero; cleared otherwise.
V-Set if an overflow is generated; cleared otherwise.
C-Set if a borrow is generated; cleared otherwise.
Description:Compares the contents of memory location to the contents of the specified register and sets the appropriate condition codes. Neither memory location M nor the specified register is modified. The carry flag represents a borrow and is set to the inverse of the resulting binary carry.
Addressing Modes:Immediate
Extended
Direct
Indexed
CMP (16-Bit)Compare Memory from RegisterCMP (16-Bit)
Source Forms:CMPD P; CMPX P; CMPY P; CMPU P; CMPS P
Operation:TEMP ← R - M:M+1
Condition Codes:
H-Not affected.
N-Set if the result is negative; cleared otherwise.
Z-Set if the result is zero; cleared otherwise.
V-Set if an overflow is generated; cleared otherwise.
C-Set if a borrow is generated; cleared otherwise.
Description:Compares the 16-bit contents of the concatenated memory locations M:M+1 to the contents of the specified register and sets the appropriate condition codes. Neither the memory locations nor the specified register is modified unless autoincrement or autodecrement are used. The carry flag represents a borrow and is set to the inverse of the resulting binary carry.
Addressing Modes:Immediate
Extended
Direct
Indexed
COMComplementCOM
Source Forms:COM Q; COMA; COMB
Operation:M' ← 0 + M
Condition Codes:
H-Not affected.
N-Set if the result is negative; cleared otherwise.
Z-Set if the result is zero; cleared otherwise.
V-Always cleared.
C-Always set.
Description:Replaces the contents of memory location M or accumulator A or B with its logical complement. When operating on unsigned values, only BEQ and BNE branches can be expected to behave properly following a COM instruction. When operating on twos complement values, all signed branches are available.
Addressing Modes:Inherent
Extended
Direct
Indexed
CWAIClear CC bits and Wait for InterruptCWAI
Source Form:
CWAI #$XX EFHI NZVC
Operation:CCR ← CCR ∧ MI (Possibly clear masks)
Set E (entire state saved)
SP' ← SP-1, (SP) ← PCL
SP' ← SP-1, (SP) ← PCH
SP' ← SP-1, (SP) ← USL
SP' ← SP-1, (SP) ← USH
SP' ← SP-1, (SP) ← IYL
SP' ← SP-1, (SP) ← IYH
SP' ← SP-1, (SP) ← IXL
SP' ← SP-1, (SP) ← IXH
SP' ← SP-1, (SP) ← DPR
SP' ← SP-1, (SP) ← ACCB
SP' ← SP-1, (SP) ← ACCA
SP' ← SP-1, (SP) ← CCR
Condition Codes:Affected according to the operation.
Description:This instruction ANDs an immediate byte with the condition code register which may clear the interrupt mask bits I and F, stacks the entire machine state on the hardware stack and then looks for an interrupt. When a non-masked interrupt occurs, no further machine state information need be saved before vectoring to the interrupt handling routine. This instruction replaced the MC6800 CLI WAI sequence, but does not place the buses in a high-impedance state. A FIRQ (fast interrupt request) may enter its interrupt handler with its entire machine state saved. The RTI (return from interrupt) instruction will automatically return the entire machine state after testing the E (entire) bit of the recovered condition code register.
Addressing Mode:Immediate
Comments:The following immediate values will have the following results:
FF = enable neither
EF = enable IRQ
BF = enable FIRQ
AF = enable both
DAADecimal Addition AdjustDAA
Source Form:DAA
Operation:ACCA' ← ACCA + CF(MSN):CF(LSN)
where CF is a Correction Factor, as follows: the CF for each nibble (BCD) digit is determined separately, and is either 6 or 0.
Least Significant Nibble
CF(LSN) = 6 IFF 1)C = 1
or 2)LSN > 9
Most Significant Nibble
CF(MSN) = 6 IFF 1)C = 1
or 2)MSN > 9
or 3)MSN > 8 and LSN > 9
Condition Codes:
H-Not affected.
N-Set if the result is negative; cleared otherwise.
Z-Set if the result is zero; cleared otherwise.
V-Undefined.
C-Set if a carry is generated or if the carry bit was set before the operation; cleared otherwise.
Description:The sequence of a single-byte add instruction on accumulator A (either ADDA or ADCA) and a following decimal addition adjust instruction results in a BCD addition with an appropriate carry bit. Both values to be added must be in proper BCD form (each nibble such that: 0 ≤ nibble ≤ 9). Multiple-precision addition must add the carry generated by this decimal addition adjust into the next higher digit during the add operation (ADCA) immediately prior to the next decimal addition adjust.
Addressing Mode:Inherent
DECDecrementDEC
Source Forms:DEC Q; DECA; DECB
Operation:M' ← M - 1
Condition Codes:
H-Not affected.
N-Set if the result is negative; cleared otherwise.
Z-Set if the result is zero; cleared otherwise.
V-Set if the original operand was 100000002; cleared otherwise.
C-Not affected.
Description:Subtract one from the operand. The carry bit is not affected, thus allowing this instruction to be used as a loop counter in multiple-precision computations. When operating on unsigned values, only BEQ and BNE branches can be expected to behave consistently. When operating on twos complement values, all signed branches are available.
Addressing Modes:Inherent
Extended
Direct
Indexed
EORExclusive OREOR
Source Forms:EORA P; EORB P
Operation:R' ← R ⊕ M
Condition Codes:
H-Not affected.
N-Set if the result is negative; cleared otherwise.
Z-Set if the result is zero; cleared otherwise.
V-Always cleared.
C-Not affected.
Description:The contents of memory location M is exclusive ORed into an 8-bit register.
Addressing Modes:Immediate
Extended
Direct
Indexed
EXGExchange RegistersEXG
Source Form:EXG R1,R2
Operation:R1 ↔ R2
Condition Codes:Not affected (unless one of the registers is the condition code register).
Description:Exchanges data between two designated registers. Bits 3-0 of the postbyte define one register, while bits 7-4 define the other, as follows:
0000 =A:B   1000 =A
0001 =X1001 =B
0010 =Y1010 =CCR
0011 =US1011 =DPR
0100 =SP1100 =Undefined
0101 =PC1101 =Undefined
0110 =Undefined1110 =Undefined
0111 =Undefined1111 =Undefined
Only like size registers may be exchanged. (8-bit with 8-bit or 16-bit with 16-bit.)
Addressing Mode:Immediate
INCIncrementINC
Source Forms:INC Q; INCA; INCB
Operation:M' ← M + 1
Condition Codes:
H-Not affected.
N-Set if the result is negative; cleared otherwise.
Z-Set if the result is zero; cleared otherwise.
V-Set if the original operand was 011111112; cleared otherwise.
C-Not affected.
Description:Adds to the operand. The carry bit is not affected, thus allowing this instruction to be used as a loop counter in multiple-precision computations. When operating on unsigned values, only the BEQ and BNE branches can be expected to behave consistently. When operating on twos complement values, all signed branches are correctly available.
Addressing Modes:Inherent
Extended
Direct
Indexed
JMPJumpJMP
Source Form:JMP EA
Operation:PC' ← EA
Condition Codes:Not affected.
Description:Program control is transferred to the effective address.
Addressing Modes:Extended
Direct
Indexed
JSRJump to SubroutineJSR
Source Form:JSR EA
Operation:SP' ← SP-1, (SP) ← PCL
SP' ← SP-1, (SP) ← PCH
PC' ←EA
Condition Codes:Not affected.
Description:Program control is transferred to the effective address after storing the return address on the hardware stack. A RTS instruction should be the last executed instruction of the subroutine.
Addressing Modes:Extended
Direct
Indexed
LD (8-Bit)Load Register from MemoryLD (8-Bit)
Source Forms:LDA P; LDB P
Operation:R' ← M
Condition Codes:
H-Not affected.
N-Set if the loaded data is negative; cleared otherwise.
Z-Set if the loaded data is zero; cleared otherwise.
V-Always cleared.
C-Not affected.
Description:Loads the contents of memory location M into the designated register.
Addressing Modes:Immediate
Extended
Direct
Indexed
LD (16-Bit)Load Register from MemoryLD (16-Bit)
Source Forms:LDD P; LDX P; LDY P; LDS P; LDU P
Operation:R' ← M:M+1
Condition Codes:
H-Not affected.
N-Set if the loaded data is negative; cleared otherwise.
Z-Set if the loaded data is zero; cleared otherwise.
V-Always cleared.
C-Not affected.
Description:Load the contents of the memory location M:M+1 into the designated 16-bit register.
Addressing Modes:Immediate
Extended
Direct
Indexed
LEALoad Effective AddressLEA
Source Forms:LEAX, LEAY, LEAS, LEAU
Operation:R' ← EA
Condition Codes:
H-Not affected.
N-Not affected.
Z-LEAX, LEAY: Set if the result is zero; cleared otherwise.
LEAS, LEAU: Not affected.
V-Not affected.
C-Not affected.
Description:Calculates the effective address from the indexed addressing mode and places the address in an indexable register.

LEAX and LEAY affect the Z (zero) bit to allow use of these registers as counters and for MC6800 INX/DEX compatibility.

LEAU and LEAS do not affect the Z bit to allow cleaning up the stack while returning the Z bit as a parameter to a calling routine, and also for MC6800 INS/DES compatibility.
Addressing Mode:Indexed
Comments:Due to the order in which effective addresses are calculated internally, the LEAX ,X++ and LEAX ,X+ do not add 2 and 1 (respectively) to the X register; but instead leave the X register unchanged. This also applies to the Y, U, and S registers. For the expected results, use the faster instruction LEAX 2,X and LEAX 1,X.

Some examples of LEA instruction uses are given in the following table.
InstructionOperationComment
LEAX10,XX+10 → XAdds 5-bit constant 10 to X
LEAX500,XX+500 → XAdds 16-bit constant 500 to X
LEAYA,YY+A → YAdds 8-bit accumulator to Y
LEAYD,YY+D → YAdds 16-bit D accumulator to Y
LEAU-10,UU-10 → USubtracts 10 from U
LEAS-10,SS-10 → SUsed to reserve area on stack
LEAS10,SS+10 → SUsed to 'clean up' stack
LEAX5,SS+5 → XTransfers as well as adds
LSLLogical Shift LeftLSL
Source Forms:LSL Q; LSLA; LSLB
Operation:
C           0
b7b0
Condition Codes:
H-Undefined.
N-Set if the result is negative; cleared otherwise.
Z-Set if the result is zero; cleared otherwise.
V-Loaded with the result of the exclusive OR of bits six and seven of the original operand.
C-Loaded with bit seven of the original operand.
Description:Shifts all bits of accumulator A or B or memory location M one place to the left. Bit zero is loaded with a zero. Bit seven of accumulator A or B or memory location M is shifted into the C (carry) bit.
Addressing Modes:Inherent
Extended
Direct
Indexed
Comments:This is a duplicate assembly-language mnemonic for the single machine instruction ASL.
LSRLogical Shift RightLSR
Source Forms:LSR Q; LSRA; LSRB
Operation:
0           C
b7b0
Condition Codes:
H-Not affected.
N-Always cleared.
Z-Set if the result is zero; cleared otherwise.
V-Not affected.
C-Loaded with bit zero of the original operand.
Description:Performs a logical shift right on the operand. Shifts a zero into bit seven and bit zero into the C (carry) bit.
Addressing Modes:Inherent
Extended
Direct
Indexed
MULMultiplyMUL
Source Form:MUL
Operation:ACCA':ACCB' ← ACCA × ACCB
Condition Codes:
H-Not affected.
N-Not affected.
Z-Set if the result is zero; cleared otherwise.
V-Not affected.
C-Set if ACCB bit 7 of result is set; cleared otherwise.
Description:Multiply the unsigned binary numbers in the accumulators and place the result in both accumulators (ACCA contains the most-significant byte of the result). Unsigned multiply allows multiple-precision operations.
Addressing Mode:Inherent
Comments:The C (carry) bit allows rounding the most-significant byte through the sequence: MUL, ADCA #0.
NEGNegateNEG
Source Forms:NEG Q; NEGA; NEG B
Operation:M' ← 0 - M
Condition Codes:
H-Undefined.
N-Set if the result is negative; cleared otherwise.
Z-Set if the result is zero; cleared otherwise.
V-Set if the original operand was 100000002.
C-Set if a borrow is generated; cleared otherwise.
Description:Replaces the operand with its twos complement. The C (carry) bit represents a borrow and is set to the inverse of the resulting binary carry. Note that 8016 is replaced by itself and only in this case is the V (overflow) bit set. The value 0016 is also replaced by itself, and only in this case is the C (carry) bit cleared.
Addressing Modes:Inherent
Extended
Direct
NOPNo OperationNOP
Source Form:NOP
Operation:Not affected.
Condition Codes:This instruction causes only the program counter to be incremented. No other registers or memory locations are affected.
Addressing Mode:Inherent
ORInclusive OR Memory into RegisterOR
Source Forms:ORA P; ORB P
Operation:R' ← R ∨ M
Condition Codes:
H-Not affected.
N-Set if the result is negative; cleared otherwise.
Z-Set if the result is zero; cleared otherwise.
V-Always cleared.
C-Not affected.
Description:Performs an inclusive OR operation between the contents of accumulator A or B and the contents of memory location M and the result is stored in accumulator A or B.
Addressing Modes:Immediate
Extended
Direct
Indexed
ORInclusive OR Memory Immediate into Condition Code RegisterOR
Source Form:ORCC #XX
Operation:R' ← R ∨ MI
Condition Codes:Affected according to the operation.
Description:Performs an inclusive OR operation between the contents of the condition code registers and the immediate value, and the result is placed in the condition code register. This instruction may be used to set interrupt masks (disable interrupts) or any other bit(s).
Addressing Mode:Immediate
PSHSPush Registers on the Hardware StackPSHS
Source Form:PSHS register list
PSHS #LABEL
Postbyte:
b7b6b5b4 b3b2b1b0
PCUYX DPBACC
push order →
Operation:
IFF b7 of postbyte set, then:SP' ← SP-1, (SP) ← PCL
SP' ← SP-1, (SP) ← PCH
IFF b6 of postbyte set, then:SP' ← SP-1, (SP) ← USL
SP' ← SP-1, (SP) ← USH
IFF b5 of postbyte set, then:SP' ← SP-1, (SP) ← IYL
SP' ← SP-1, (SP) ← IYH
IFF b4 of postbyte set, then:SP' ← SP-1, (SP) ← IXL
SP' ← SP-1, (SP) ← IXH
IFF b3 of postbyte set, then:SP' ← SP-1, (SP) ← DPR
IFF b2 of postbyte set, then:SP' ← SP-1, (SP) ← ACCB
IFF b1 of postbyte set, then:SP' ← SP-1, (SP) ← ACCA
IFF b0 of postbyte set, then:SP' ← SP-1, (SP) ← CCR
Condition Codes:Not affected.
Description:All, some, or none of the processor registers are pushed onto the hardware stack (with the exception of the hardware stack pointer itself).
Addressing Mode:Immediate
Comments:A single register may be placed on the stack with the condition codes set by doing an autodecrement store onto the stack (example: STX ,--S).
PSHUPush Registers on the User StackPSHU
Source Form:PSHU register list
PSHU #LABEL
Postbyte:
b7b6b5b4 b3b2b1b0
PCSYX DPBACC
push order →
Operation:
IFF b7 of postbyte set, then:US' ← US-1, (US) ← PCL
US' ← US-1, (US) ← PCH
IFF b6 of postbyte set, then:US' ← US-1, (US) ← SPL
US' ← US-1, (US) ← SPH
IFF b5 of postbyte set, then:US' ← US-1, (US) ← IYL
US' ← US-1, (US) ← IYH
IFF b4 of postbyte set, then:US' ← US-1, (US) ← IXL
US' ← US-1, (US) ← IXH
IFF b3 of postbyte set, then:US' ← US-1, (US) ← DPR
IFF b2 of postbyte set, then:US' ← US-1, (US) ← ACCB
IFF b1 of postbyte set, then:US' ← US-1, (US) ← ACCA
IFF b0 of postbyte set, then:US' ← US-1, (US) ← CCR
Condition Codes:Not affected.
Description:All, some, or none of the processor registers are pushed onto the user stack (with the exception of the user stack pointer itself).
Addressing Mode:Immediate
Comments:A single register may be placed on the stack with the condition codes set by doing an autodecrement store onto the stack (example: STX ,--U).
PULSPull Registers from the Hardware StackPULS
Source Form:PULS register list
PULS #LABEL
Postbyte:
b7b6b5b4 b3b2b1b0
PCUYX DPBACC
← pull order
Operation:
IFF b0 of postbyte set, then:CCR'← (SP), SP' ← SP+1
IFF b1 of postbyte set, then:ACCA'← (SP), SP' ← SP+1
IFF b2 of postbyte set, then:ACCB'← (SP), SP' ← SP+1
IFF b3 of postbyte set, then:DPR'← (SP), SP' ← SP+1
IFF b4 of postbyte set, then:IXH'
IXL'
← (SP), SP' ← SP+1
← (SP), SP' ← SP+1
IFF b5 of postbyte set, then:IYH'
IYL'
← (SP), SP' ← SP+1
← (SP), SP' ← SP+1
IFF b6 of postbyte set, then:USH'
USL'
← (SP), SP' ← SP+1
← (SP), SP' ← SP+1
IFF b7 of postbyte set, then:PCH'
PCL'
← (SP), SP' ← SP+1
← (SP), SP' ← SP+1
Condition Codes:May be pulled from stack; not affected otherwise.
Description:All, some, or none of the processor registers are pulled from the hardware stack (with the exception of the hardware stack pointer itself).
Addressing Mode:Immediate
Comments:A single register may be pulled from the stack with condition codes set by doing an autoincrement load from the stack (example: LDX ,S++).
PULUPull Registers from the User StackPULU
Source Form:PULU register list
PULU #LABEL
Postbyte:
b7b6b5b4 b3b2b1b0
PCSYX DPBACC
← pull order
Operation:
IFF b0 of postbyte set, then:CCR'← (US), US' ← US+1
IFF b1 of postbyte set, then:ACCA'← (US), US' ← US+1
IFF b2 of postbyte set, then:ACCB'← (US), US' ← US+1
IFF b3 of postbyte set, then:DPR'← (US), US' ← US+1
IFF b4 of postbyte set, then:IXH'
IXL'
← (US), US' ← US+1
← (US), US' ← US+1
IFF b5 of postbyte set, then:IYH'
IYL'
← (US), US' ← US+1
← (US), US' ← US+1
IFF b6 of postbyte set, then:SPH'
SPL'
← (US), US' ← US+1
← (US), US' ← US+1
IFF b7 of postbyte set, then:PCH'
PCL'
← (US), US' ← US+1
← (US), US' ← US+1
Condition Codes:May be pulled from stack; not affected otherwise.
Description:All, some, or none of the processor registers are pulled from the user stack (with the exception of the user stack pointer itself).
Addressing Mode:Immediate
Comments:A single register may be pulled from the stack with condition codes set by doing an autoincrement load from the stack (example: LDX ,U++).
ROLRotate LeftROL
Source Forms:ROL Q; ROLA; ROLB
Operation:
C           C
b7b0
Condition Codes:
H-Not affected.
N-Set if the result is negative; cleared otherwise.
Z-Set if the result is zero; cleared otherwise.
V-Loaded with the result of the exclusive OR of bits six and seven of the original operand.
C-Loaded with bit seven of the original operand.
Description:Rotates all bits of the operand one place left through the C (carry) bit. This is a 9-bit rotation.
Addressing Mode:Inherent
Extended
Direct
Indexed
RORRotate RightROR
Source Forms:ROR Q; RORA; RORB
Operation:
C           C
b7b0
Condition Codes:
H-Not affected.
N-Set if the result is negative; cleared otherwise.
Z-Set if the result is zero; cleared otherwise.
V-Not affected.
C-Loaded with bit zero of the previous operand.
Description:Rotates all bits of the operand one place right through the C (carry) bit. This is a 9-bit rotation.
Addressing Modes:Inherent
Extended
Direct
Indexed
RTIReturn from InterruptRTI
Source Form:RTI
Operation:CCR' ← (SP), SP' ← SP+1, then
IFF CCR bit E is set, then: ACCA'
ACCB'
DPR'
IXH'
IXL'
IYH'
IYL'
USH'
USL'
PCH'
PCL'
← (SP), SP' ← SP+1
← (SP), SP' ← SP+1
← (SP), SP' ← SP+1
← (SP), SP' ← SP+1
← (SP), SP' ← SP+1
← (SP), SP' ← SP+1
← (SP), SP' ← SP+1
← (SP), SP' ← SP+1
← (SP), SP' ← SP+1
← (SP), SP' ← SP+1
← (SP), SP' ← SP+1
IFF CCR bit E is clear, then: PCH'
PCL'
← (SP), SP' ← SP+1
← (SP), SP' ← SP+1
Condition Codes:Recovered from the stack.
Description:The saved machine state is recovered from the hardware stack and control is returned to the interrupted program. If the recovered E (entire) bit is clear, it indicates that only a subset of the machine state was saved (return address and condition codes) and only that subset is recovered.
Addressing Mode:Inherent
RTSReturn from SubroutineRTS
Source Form:RTS
Operation:PCH' ← (SP), SP' ← SP+1
PCL' ← (SP), SP' ← SP+1
Condition Codes:Not affected.
Description:Program control is returned from the subroutine to the calling program. The return address is pulled from the stack.
Addressing Mode:Inherent
SBCSubtract with BorrowSBC
Source Forms:SBCA P; SBCB P
Operation:R' ← R - M - C
Condition Codes:
H-Undefined.
N-Set if the result is negative; cleared otherwise.
Z-Set if the result is zero; cleared otherwise.
V-Set if an overflow is generated; cleared otherwise.
C-Set if a borrow is generated; cleared otherwise.
Description:Subtracts the contents of memory location M and the borrow (in the C (carry) bit) from the contents of the designated 8-bit register, and places the result in that register. The C bit represents a borrow and is set to the inverse of the resulting binary carry.
Addressing Modes:Immediate
Extended
Direct
Indexed
SEXSign ExtendedSEX
Source Form:SEX
Operation:If bit seven of ACCB is set then ACCA' ← FF16 else ACCA' ← 0016
Condition Codes:
H-Not affected.
N-Set if the result is negative; cleared otherwise.
Z-Set if the result is zero; cleared otherwise.
V-Not affected.
C-Not affected.
Description:This instruction transforms a twos complement 8-bit value in accumulator B into a twos complement 16-bit value in the D accumulator.
Addressing Mode:Inherent
ST (8-Bit)Store Register into MemoryST (8-Bit)
Source Forms:STA P; STB P
Operation:M' ← R
Condition Codes:
H-Not affected.
N-Set if the result is negative; cleared otherwise.
Z-Set if the result is zero; cleared otherwise.
V-Always cleared.
C-Not affected.
Description:Writes the contents of an 8-bit register into a memory location.
Addressing Modes:Extended
Direct
Indexed
ST (16-Bit)Store Register into MemoryST (16-Bit)
Source Forms:STD P; STX P; STY P; STS P; STU P
Operation:M':M+1' ← R
Condition Codes:
H-Not affected.
N-Set if the result is negative; cleared otherwise.
Z-Set if the result is zero; cleared otherwise.
V-Always cleared.
C-Not affected.
Description:Writes the contents of a 16-bit register into two consecutive memory locations.
Addressing Modes:Extended
Direct
Indexed
SUB (8-Bit)Subtract Memory from RegisterSUB (8-Bit)
Source Forms:SUBA P; SUBB P
Operation:R' ← R - M
Condition Codes:
H-Undefined.
N-Set if the result is negative; cleared otherwise.
Z-Set if the result is zero; cleared otherwise.
V-Set if the overflow is generated; cleared otherwise.
C-Set if a borrow is generated; cleared otherwise.
Description:Subtracts the value in memory location M from the contents of a designated 8-bit register. The C (carry) bit represents a borrow and is set to the inverse of the resulting binary carry.
Addressing Modes:Immediate
Extended
Direct
Indexed
SUB (16-Bit)Subtract Memory from RegisterSUB (16-Bit)
Source Forms:SUBD P
Operation:R' ← R - M:M+1
Condition Codes:
H-Not affected.
N-Set if the result is negative; cleared otherwise.
Z-Set if the result is zero; cleared otherwise.
V-Set if the overflow is generated; cleared otherwise.
C-Set if a borrow is generated; cleared otherwise.
Description:Subtracts the value in memory location M:M+1 from the contents of a designated 16-bit register. The C (carry) bit represents a borrow and is set to the inverse of the resulting binary carry.
Addressing Modes:Immediate
Extended
Direct
Indexed
SWISoftware InterruptSWI
Source Form:SWI
Operation:Set E (entire state will be saved)
SP' ← SP-1, (SP) ← PCL
SP' ← SP-1, (SP) ← PCH
SP' ← SP-1, (SP) ← USL
SP' ← SP-1, (SP) ← USH
SP' ← SP-1, (SP) ← IYL
SP' ← SP-1, (SP) ← IYH
SP' ← SP-1, (SP) ← IXL
SP' ← SP-1, (SP) ← IXH
SP' ← SP-1, (SP) ← DPR
SP' ← SP-1, (SP) ← ACCB
SP' ← SP-1, (SP) ← ACCA
SP' ← SP-1, (SP) ← CCR
Set I, F (mask interrupts)
PC' ← (FFFA):(FFFB)
Condition Codes:Not affected.
Description:All of the processor registers are pushed onto the hardware stack (with the exception of the hardware stack pointer itself), and control is transferred through the software interrupt vector. Both the normal and fast interrupts are masked (disabled).
Addressing Mode:Inherent
SWI2Software Interrupt 2SWI2
Source Form:SWI2
Operation:Set E (entire state saved)
SP' ← SP-1, (SP) ← PCL
SP' ← SP-1, (SP) ← PCH
SP' ← SP-1, (SP) ← USL
SP' ← SP-1, (SP) ← USH
SP' ← SP-1, (SP) ← IYL
SP' ← SP-1, (SP) ← IYH
SP' ← SP-1, (SP) ← IXL
SP' ← SP-1, (SP) ← IXH
SP' ← SP-1, (SP) ← DPR
SP' ← SP-1, (SP) ← ACCB
SP' ← SP-1, (SP) ← ACCA
SP' ← SP-1, (SP) ← CCR
PC' ← (FFF4):(FFF5)
Condition Codes:Not affected.
Description:All of the processor registers are pushed onto the hardware stack (with the exception of the hardware stack pointer itself), and control is transferred through the software interrupt 2 vector. This interrupt is available to the end user and must not be used in packaged software. This interrupt does not mask (disable) the normal and fast interrupts.
Addressing Mode:Inherent
SWI3Software Interrupt 3SWI3
Source Form:SWI3
Operation:Set E (entire state will be saved)
SP' ← SP-1, (SP) ← PCL
SP' ← SP-1, (SP) ← PCH
SP' ← SP-1, (SP) ← USL
SP' ← SP-1, (SP) ← USH
SP' ← SP-1, (SP) ← IYL
SP' ← SP-1, (SP) ← IYH
SP' ← SP-1, (SP) ← IXL
SP' ← SP-1, (SP) ← IXH
SP' ← SP-1, (SP) ← DPR
SP' ← SP-1, (SP) ← ACCB
SP' ← SP-1, (SP) ← ACCA
SP' ← SP-1, (SP) ← CCR
PC' ← (FFF2):(FFF3)
Condition Codes:Not affected.
Description:All of the processor registers are pushed onto the hardware stack (with the exception of the hardware stack pointer itself), and control is transferred through the software interrupt 3 vector. This interrupt does not mask (disable) the normal and fast interrupts.
Addressing Mode:Inherent
SYNCSynchronize to External EventSYNC
Source Form:SYNC
Operation:Stop processing instructions
Condition Codes:Not affected.
Description:When a SYNC instruction is excuted, the processor enters a synchronizing state, stops processing instructions, and waits for an interrupt. When an interrupt occurs, the synchronizing state is cleared and processing continues. If the interrupt is enabled, and it lasts three cycles or more, the processor will perform the interrupt routine. If the interrupt is masked or is shorter than three cycles, the processor simply continues to the next instruction. While in the synchronizing state, the address and data buses are in the high-impedance state.

This instruction provides software synchronization with a hardware process. Consider the following example for high-speed acquisition of data:
FASTSYNCWAIT FOR DATA
Interrupt!
LDADISCDATA FROM DISC AND CLEAR INTERRUPT
STA,X+PUT IN BUFFER
DECBCOUNT IT, DONE?
BNEFASTGO AGAIN IF NOT.
The synchronizing state is cleared by any interrupt. Of course, enabled interrupts at this point may destroy the data transfer and, as such, should represent only emergency conditions.

The same connection used for interrupt-driven I/O service may also be used for high-speed data transfers by setting the interrupt mask and using the SYNC instruction as the above example demonstrates.
Addressing Mode:Inherent
TFRTransfer Register to RegisterTFR
Source Form:TFR R1, R2
Operation:R1 → R2
Condition Codes:Not affected unless R2 is the condition code register.
Description:Transfers data between two designated registers. Bits 7-4 of the postbyte define the source register, while bits 3-0 define the destination register, as follows:
0000 =A:B   1000 =A
0001 =X1001 =B
0010 =Y1010 =CCR
0011 =US1011 =DPR
0100 =SP1100 =Undefined
0101 =PC1101 =Undefined
0110 =Undefined1110 =Undefined
0111 =Undefined1111 =Undefined
Only like size registers may be transferred. (8-bit to 8-bit, or 16-bit to 16-bit.)
Addressing Mode:Immediate
TSTTestTST
Source Forms:TST Q; TSTA; TSTB
Operation:TEMP ← M - 0
Condition Codes:
H-Not affected.
N-Set if the result is negative; cleared otherwise.
Z-Set if the result is zero; cleared otherwise.
V-Always cleared.
C-Not affected.
Description:Set the N (negative) and Z (zero) bits according to the contents of memory location M, and clear the V (overflow) bit. The TST instruction provides only minimum information when testing unsigned values; since no unsigned value is less than zero, BLO and BLS have no utility. While BHI could be used after TST, it provides exactly the same control as BNE, which is preferred. The signed branches are available.
Addressing Modes:Inherent
Extended
Direct
Indexed
Comments:The MC6800 processor clears the C (carry) bit.
FIRQFast Interrupt Request (Hardware Interrupt)FIRQ
Operation:
IFF F bit clear, then:SP' ← SP-1, (SP) ← PCL
SP' ← SP-1, (SP) ← PCH
Clear E (subset state is saved)
SP' ← SP-1, (SP) ← CCR
Set F, I (mask further interrupts)
PC' ← (FFF6):(FFF7)
Condition Codes:Not affected.
Description:A FIRQ (fast interrupt request) with the F (fast interrupt request mask) bit clear causes this interrupt sequence to occur at the end of the current instruction. The program counter and condition code register are pushed onto the hardware stack. Program control is transferred through the fast interrupt request vector. An RTI (return from interrupt) instruction returns the processor to the original task. It is possible to enter the fast interrupt request routine with the entire machine state saved if the fast interrupt request occurs after a clear and wait for interrupt instruction. A normal interrupt request has lower priority than the fast interrupt request and is prevented from interrupting the fast interrupt request routine by automatic setting of the I (interrupt request mask) bit. This mask bit could then be reset during the interrupt routine if priority was not desired. The fast interrupt request allows operations on memory, TST, INC, DEC, etc. instructions without the overhead of saving the entire machine state on the stack.
Addressing Mode:Inherent
IRQInterrupt Request (Hardware Interrupt)IRQ
Operation:
IFF I bit clear, then:SP' ← SP-1, (SP) ← PCL
SP' ← SP-1, (SP) ← PCH
SP' ← SP-1, (SP) ← USL
SP' ← SP-1, (SP) ← USH
SP' ← SP-1, (SP) ← IYL
SP' ← SP-1, (SP) ← IYH
SP' ← SP-1, (SP) ← IXL
SP' ← SP-1, (SP) ← IXH
SP' ← SP-1, (SP) ← DPR
SP' ← SP-1, (SP) ← ACCB
SP' ← SP-1, (SP) ← ACCA
Set E (entire state saved)
SP' ← SP-1, (SP) ← CCR
Set I (mask further IRQ interrupts)
PC' ← (FFF8):(FFF9)
Condition Codes:Not affected.
Description:If the I (interrupt request mask) bit is clear, a low level on the IRQ input causes this interrupt sequence to occur at the end of the current instruction. Control is returned to the interrupted program using a RTI (return from interrupt) instruction. A FIRQ (fast interrupt request) may interrupt a normal IRQ (interrupt request) routine and be recognized anytime after the interrupt vector is taken.
Addressing Mode:Inherent
NMINon-Maskable Interrupt (Hardware Interrupt)NMI
Operation:SP' ← SP-1, (SP) ← PCL
SP' ← SP-1, (SP) ← PCH
SP' ← SP-1, (SP) ← USL
SP' ← SP-1, (SP) ← USH
SP' ← SP-1, (SP) ← IYL
SP' ← SP-1, (SP) ← IYH
SP' ← SP-1, (SP) ← IXL
SP' ← SP-1, (SP) ← IXH
SP' ← SP-1, (SP) ← DPR
SP' ← SP-1, (SP) ← ACCB
SP' ← SP-1, (SP) ← ACCA
Set E (entire state save)
SP' ← SP-1, (SP) ← CCR
Set I, F (mask interrupts)
PC' ← (FFFC):(FFFD)
Condition Codes:Not affected.
Description:A negative edge on the NMI (non-maskable interrupt) input causes all of the processor's registers (except the hardware stack pointer) to be pushed onto the hardware stack, starting at the end of the current instruction. Program control is transferred through the NMI vector. Successive negative edges on the NMI input will cause successive NMI operations. Non-maskable interrupt operation can be internally blocked by a RESET operation and any non-maskable interrupt that occurs will be latched. If this happens, the non-maskable interrupt operation will occur after the first load into the stack pointer (LDS; TFR r,s; EXG r,s; etc.) after RESET.
Addressing Mode:Inherent
RESTARTRestart (Hardware Interrupt)RESTART
Operation:CCR' ← X1X1XXXX
DPR' ← 0016
PC' ← (FFFE):(FFFF)
Condition Codes:Not affected.
Description:The processor is initialized (required after power-on) to start program execution. The starting address is fetched from the restart vector.
Addressing Mode:Extended Indirect

© Motorola Inc., 1981 (now Freescale as of 2006)
Transferred into HTML by Matthias "Maddes" Bücher in 2006, 2007.
Use all information at your own risk.

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