MC6809-MC6809E 8-Bit Microprocessor Programming Manual [M6809PM/AD]
© Motorola Inc., 1981
This appendix contains the opcode map and additional information for calculating required machine cycles.
Table F-1 is the opcode map for M6809 processors. The number(s) by each instruction indicates the number of machine cycles required to execute that instruction.
When the number contains an "I" (e.g., 4+I), it indicates that the indexed addressing mode is being used and that an additional number of machine cycles may be required.
Refer to Table F-2 to determine the additional machine cycles to be added.
Some instructions in the opcode map have two numbers, the second one in parenthesis.
This indicates that the instruction involves a branch.
The parenthetical number applies if the branch is taken.
The "page 2, page 3" notation in column one means that all page 2 instructions are preceded by a hexadecimal 10 opcode and all page 3 instructions are preceded by a hexadecimal 11 opcode.
Table F-2. Indexed Addressing Mode Data
Type |
Forms |
Non Indirect |
Indirect |
Assembler Form |
Postbyte OP Code |
× ~ |
+ # |
Assembler Form |
Postbyte OP Code |
× ~ |
+ # |
Constant Offset From R (twos complement offset) |
No Offset |
,R |
1RR00100 |
0 |
0 |
[,R] |
1RR10100 |
3 |
0 |
5-Bit Offset |
n, R |
0RRnnnnn |
1 |
0 |
defaults to 8-bit |
|
|
8-Bit Offset |
n, R |
1RR01000 |
1 |
1 |
[n, R] |
1RR11000 |
4 |
1 |
16-Bit Offset |
n, R |
1RR01001 |
4 |
2 |
[n, R] |
1RR11001 |
7 |
2 |
Accumulator Offset From R (twos complement offset) |
A - Register Offset |
A, R |
1RR00110 |
1 |
0 |
[A, R] |
1RR10110 |
4 |
0 |
B - Register Offset |
B, R |
1RR00101 |
1 |
0 |
[B, R] |
1RR10101 |
4 |
0 |
D - Register Offset |
D, R |
1RR01011 |
4 |
0 |
[D, R] |
1RR11011 |
7 |
0 |
Auto Increment/Decrement R |
Increment by 1 |
,R+ |
1RR00000 |
2 |
0 |
not allowed |
|
|
Increment by 2 |
,R++ |
1RR00001 |
3 |
0 |
[,R++] |
1RR10001 |
6 |
0 |
Decrement by 1 |
,-R |
1RR00010 |
2 |
0 |
not allowed |
|
|
Decrement by 2 |
,--R |
1RR00011 |
3 |
0 |
[,--R] |
1RR10011 |
6 |
0 |
Constant Offset From PC (twos complement offset) |
8-Bit Offset |
n, PCR |
1XX01100 |
1 |
1 |
[n, PCR] |
1XX11100 |
4 |
1 |
16-Bit Offset |
n, PCR |
1XX01101 |
5 |
2 |
[n, PCR] |
1XX11101 |
8 |
2 |
Extended Indirect |
16-Bit Address |
- |
- |
- |
- |
[n] |
10011111 |
5 |
2 |
|
R = X, Y, U or S X = Don't Care |
X = 00 U = 10 |
Y = 01 S = 11 |
|
× ~ |
and |
+ # |
indicate the number of additional cycles and bytes for the particular variation. |
© Motorola Inc., 1981 (now Freescale as of 2006)
Transformed into HTML by Matthias "Maddes" Bücher in 2006, 2007, 2023.
Use all information at your own risk.