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MC6809-MC6809E 8-Bit Microprocessor Programming Manual [M6809PM/AD]
© Motorola Inc., 1981

APPENDIX F - OPCODE MAP

F.1 INTRODUCTION

This appendix contains the opcode map and additional information for calculating required machine cycles.

F.2 OPCODE MAP

Table F-1 is the opcode map for M6809 processors. The number(s) by each instruction indicates the number of machine cycles required to execute that instruction. When the number contains an "I" (e.g., 4+I), it indicates that the indexed addressing mode is being used and that an additional number of machine cycles may be required. Refer to Table F-2 to determine the additional machine cycles to be added.

Some instructions in the opcode map have two numbers, the second one in parenthesis. This indicates that the instruction involves a branch. The parenthetical number applies if the branch is taken.

The "page 2, page 3" notation in column one means that all page 2 instructions are preceded by a hexadecimal 10 opcode and all page 3 instructions are preceded by a hexadecimal 11 opcode.

Table F-1. Opcode Map
Most-Significant Four Bits
DIR REL ACCA ACCB IND EXT IMM DIR IND EXT IMM DIR IND EXT
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
0 1 2 3 4 5 6 7 8 9 A B C D E F
Least
Signi-
ficant
Four
Bits		 0000 0 6
NEG		 PAGE2 3 BRA 4+1
LEAX		 2 2 6+1 7 2 4 4+1 5 2 4 4+1 5 0
NEG SUBA SUBB
0001 1 - PAGE3 3 BRN /
5 LBRN		 4+1
LEAY		 - 2 4 4+1 5 2 4 4+1 5 1
CMPA CMPB
0010 2 - 2
NOP		 3 BHI /
5(6) LBHI		 4+1
LEAS		 - 2 4 4+1 5 2 4 4+1 5 2
SBCA SBCB
0011 3 6
COM		 2
SYNC		 3 BLS /
5(6) LBLS		 4+1
LEAU		 2 2 6+1 7
4, 6, 6+1, 7 / 5, 7, 7+1, 8 / 5, 7, 7+1, 8
SUBD CMPD CMPU
4 6 6+1 7 3
COM ADDD
0100 4 6
LSR		 - 3 BHS
5(6) (BCC)		 5+1/byte
PSHS		 2 2 6+1 7 2 4 4+1 5 2 4 4+1 5 4
LSR ANDA ANDB
0101 5 - - 3 BLO
5(6) (BCS)		 5+1/byte
PULS		 - 2 4 4+1 5 2 4 4+1 5 5
BITA BITB
0110 6 6
ROR		 5
LBRA		 3 BNE /
5(6) LBNE		 5+1/byte
PSHU		 2 2 6+1 7 2 4 4+1 5 2 4 4+1 5 6
ROR LDA LDB
0111 7 6
ASR		 9
LBSR		 3 BEQ /
5(6) LBEQ		 5+1/byte
PULU		 2 2 6+1 7 - 4 4+1 5 - 4 4+1 5 7
ASR STA STB
1000 8 6 ASL
(LSL)		 - 3 BVC /
5(6) LBVC		 - 2 2 6+1 7 2 4 4+1 5 2 4 4+1 5 8
ASL (LSL) EORA EORB
1001 9 6
ROL		 2
DAA		 3 BVS /
5(6) LBVS		 5
RTS		 2 2 6+1 7 2 4 4+1 5 2 4 4+1 5 9
ROL ADCA ADCB
1010 A 6
DEC		 3
ORCC		 3 BPL /
5(6) LBPL		 3
ABX		 2 2 6+1 7 2 4 4+1 5 2 4 4+1 5 A
DEC ORA ORB
1011 B - - 3 BMI /
5(6) LBMI		 6/15
RTI		 - 2 4 4+1 5 2 4 4+1 5 B
ADDA ADDB
1100 C 6
INC		 3
ANDCC		 3 BGE /
5(6) LBGE		 20
CWAI		 2 2 6+1 7
4, 6, 6+1, 7 / 5, 7, 7+1, 8 / 5, 7, 7+1, 8
CMPX CMPY CMPS
3 5 5+1 6 C
INC LDD
1101 D 6
TST		 2
SEX		 3 BLT /
5(6) LBLT		 11
MUL		 2 2 6+1 7 7 7 7+1 8 - 5 5+1 6 D
TST BSR JSR STD
1110 E 3
JMP		 8
EXG		 3 BGT /
5(6) LBGT		 - - 3+1 4
3, 5, 5+1, 6 / 4, 6, 6+1, 7
LDX LDY
3, 5, 5+1, 6 / 4, 6, 6+1, 7
LDU LDS
E
JMP
1111 F 6
CLR		 7
TFR		 3 BLE /
5(6) LBLE		 19/20/20
SWI/2/3		 2 2 6+1 7 -
5, 5+1, 6 / 6, 6+1, 7
STX STY
-
5, 5+1, 6 / 6, 6+1, 7
STU STS
F
CLR

Table F-2. Indexed Addressing Mode Data
Type Forms Non Indirect Indirect
Assembler
Form		 Postbyte
OP Code		 ×
~		 +
#		 Assembler
Form		 Postbyte
OP Code		 ×
~		 +
#
Constant Offset From R
(twos complement offset)		 No Offset ,R 1RR00100 0 0 [,R] 1RR10100 3 0
5-Bit Offset n, R 0RRnnnnn 1 0 defaults to 8-bit
8-Bit Offset n, R 1RR01000 1 1 [n, R] 1RR11000 4 1
16-Bit Offset n, R 1RR01001 4 2 [n, R] 1RR11001 7 2
Accumulator Offset From R
(twos complement offset)		 A - Register Offset A, R 1RR00110 1 0 [A, R] 1RR10110 4 0
B - Register Offset B, R 1RR00101 1 0 [B, R] 1RR10101 4 0
D - Register Offset D, R 1RR01011 4 0 [D, R] 1RR11011 7 0
Auto Increment/Decrement R Increment by 1 ,R+ 1RR00000 2 0 not allowed
Increment by 2 ,R++ 1RR00001 3 0 [,R++] 1RR10001 6 0
Decrement by 1 ,-R 1RR00010 2 0 not allowed
Decrement by 2 ,--R 1RR00011 3 0 [,--R] 1RR10011 6 0
Constant Offset From PC
(twos complement offset)		 8-Bit Offset n, PCR 1XX01100 1 1 [n, PCR] 1XX11100 4 1
16-Bit Offset n, PCR 1XX01101 5 2 [n, PCR] 1XX11101 8 2
Extended Indirect 16-Bit Address - - - - [n] 10011111 5 2
R = X, Y, U or S
X = Don't Care		 X = 00
U = 10		 Y = 01
S = 11
×
~		 and +
#		 indicate the number of additional cycles and bytes for the particular variation.

© Motorola Inc., 1981 (now Freescale as of 2006)
Transformed into HTML by Matthias "Maddes" Bücher in 2006, 2007, 2023.
Use all information at your own risk.

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