MC6809-MC6809E 8-Bit Microprocessor Programming Manual [M6809PM/AD]
© Motorola Inc., 1981
APPENDIX D - PROGRAMMING AID
D.1 INTRODUCTION
This appendix contains a compilation of data that will assist you in programming the M6809 processor.
Refer to Table D-1.
Table D-1. Programming Aid
Legend: |
|
M |
Complement of M |
|
¦ |
Test and set if true, cleared otherwise |
OP |
Operation Code (Hexadecimal) |
|
→ |
Transfer Into |
|
• |
Not Affected |
~ |
Number of MPU Cycles |
|
H |
Half-carry (from bit 3) |
|
CC |
Condition Code Register |
# |
Number of Program Bytes |
|
N |
Negative (sign bit) |
|
: |
Concatenation |
+ |
Arithmetic Plus |
|
Z |
Zero (Reset) |
|
∨ |
Logical or |
- |
Arithmetic Minus |
|
V |
Overflow, 2's complement |
|
∧ |
Logical and |
× |
Multiply |
|
C |
Carry from ALU |
|
∀ |
Logical Exclusive or |
Branch Instructions
Instruction |
Forms |
Addressing Mode |
Description |
5 |
3 |
2 |
1 |
0 |
Relative |
OP |
~ |
# |
H |
N |
Z |
V |
C |
BCC |
BCC |
24 |
3 |
2 |
Branch C = 0 |
• |
• |
• |
• |
• |
LBCC |
10 24 |
5(6) |
4 |
Long Branch C = 0 |
• |
• |
• |
• |
• |
BCS |
BCS |
25 |
3 |
2 |
Branch C = 1 |
• |
• |
• |
• |
• |
LBCS |
10 25 |
5(6) |
4 |
Long Branch C = 1 |
• |
• |
• |
• |
• |
BEQ |
BEQ |
27 |
3 |
2 |
Branch Z = 0 |
• |
• |
• |
• |
• |
LBEQ |
10 27 |
5(6) |
4 |
Long Branch Z = 0 |
• |
• |
• |
• |
• |
BGE |
BGE |
2C |
3 |
2 |
Branch ≥ Zero |
• |
• |
• |
• |
• |
LBGE |
10 2C |
5(6) |
4 |
Long Branch ≥ Zero |
• |
• |
• |
• |
• |
BGT |
BGT |
2E |
3 |
2 |
Branch > Zero |
• |
• |
• |
• |
• |
LBGT |
10 2E |
5(6) |
4 |
Long Branch > Zero |
• |
• |
• |
• |
• |
BHI |
BHI |
22 |
3 |
2 |
Branch Higher |
• |
• |
• |
• |
• |
LBHI |
10 22 |
5(6) |
4 |
Long Branch Higher |
• |
• |
• |
• |
• |
BHS |
BHS |
24 |
3 |
2 |
Branch Higher or Same |
• |
• |
• |
• |
• |
LBHS |
10 24 |
5(6) |
4 |
Long Branch Higher or Same |
• |
• |
• |
• |
• |
BLE |
BLE |
2F |
3 |
2 |
Branch ≤ Zero |
• |
• |
• |
• |
• |
LBLE |
10 2F |
5(6) |
4 |
Long Branch ≤ Zero |
• |
• |
• |
• |
• |
BLO |
BLO |
25 |
3 |
2 |
Branch Lower |
• |
• |
• |
• |
• |
LBLO |
10 25 |
5(6) |
4 |
Long Branch Lower |
• |
• |
• |
• |
• |
BLS |
BLS |
23 |
3 |
2 |
Branch Lower or Same |
• |
• |
• |
• |
• |
LBLS |
10 23 |
5(6) |
4 |
Long Branch Lower or Same |
• |
• |
• |
• |
• |
BLT |
BLT |
2D |
3 |
2 |
Branch < Zero |
• |
• |
• |
• |
• |
LBLT |
10 2D |
5(6) |
4 |
Long Branch < Zero |
• |
• |
• |
• |
• |
BMI |
BMI |
2B |
3 |
2 |
Branch Minus |
• |
• |
• |
• |
• |
LBMI |
10 2B |
5(6) |
4 |
Long Branch Minus |
• |
• |
• |
• |
• |
BNE |
BNE |
26 |
3 |
2 |
Branch Z ≠ 0 |
• |
• |
• |
• |
• |
LBNE |
10 26 |
5(6) |
4 |
Long Branch Z ≠ 0 |
• |
• |
• |
• |
• |
BPL |
BPL |
2A |
3 |
2 |
Branch Plus |
• |
• |
• |
• |
• |
LBPL |
10 2A |
5(6) |
4 |
Long Branch Plus |
• |
• |
• |
• |
• |
BRA |
BRA |
20 |
3 |
2 |
Branch Always |
• |
• |
• |
• |
• |
LBRA |
16 |
5 |
3 |
Long Branch Always |
• |
• |
• |
• |
• |
BRN |
BRN |
21 |
3 |
2 |
Branch Never |
• |
• |
• |
• |
• |
LBRN |
10 21 |
5 |
4 |
Long Branch Never |
• |
• |
• |
• |
• |
BSR |
BSR |
8D |
7 |
2 |
Branch to Subroutine |
• |
• |
• |
• |
• |
LBSR |
17 |
9 |
3 |
Long Branch to Subroutine |
• |
• |
• |
• |
• |
BVC |
BVC |
28 |
3 |
2 |
Branch V = 0 |
• |
• |
• |
• |
• |
LBVC |
10 28 |
5(6) |
4 |
Long Branch V = 0 |
• |
• |
• |
• |
• |
BVS |
BVS |
29 |
3 |
2 |
Branch V = 1 |
• |
• |
• |
• |
• |
LBVS |
10 29 |
5(6) |
4 |
Long Branch V = 1 |
• |
• |
• |
• |
• |
Simple Branches
|
OP |
~ |
# |
BRA |
|
20 |
3 |
2 |
LBRA |
|
16 |
5 |
3 |
BRN |
|
21 |
3 |
2 |
LBRN |
|
10 21 |
5 |
4 |
BSR |
|
8D |
7 |
2 |
LBSR |
|
17 |
9 |
3 |
Simple Conditional Branches (Notes 1-4)
Test |
|
True |
OP |
|
False |
OP |
N = 1 |
|
BMI |
2B |
|
BPL |
2A |
Z = 1 |
|
BEQ |
27 |
|
BNE |
26 |
V = 1 |
|
BVS |
29 |
|
BVC |
28 |
C = 1 |
|
BCS |
25 |
|
BCC |
24 |
Signed Conditional Branches (Notes 1-4)
Test |
|
True |
OP |
|
False |
OP |
r > m |
|
BGT |
2E |
BLE |
2F |
r ≥ m |
|
BGE |
2C |
BLT |
2D |
r = m |
|
BEQ |
27 |
BNE |
26 |
r ≤ m |
|
BLE |
2F |
BGT |
2E |
r < m |
|
BLT |
2D |
BGE |
2C |
Unsigned Conditional Branches (Notes 1-4)
Test |
|
True |
OP |
|
False |
OP |
r > m |
|
BHI |
22 |
BLS |
23 |
r ≥ m |
|
BHS |
24 |
BLO |
25 |
r = m |
|
BEQ |
27 |
BNE |
26 |
r ≤ m |
|
BLS |
23 |
BHI |
22 |
r < m |
|
BLO |
25 |
BHS |
24 |
Notes:
- All conditional branches have both short and long variations.
- All short branches are 2 bytes and require 3 cycles.
- All conditional long branches are formed by prefixing the short branch opcode with $10 and using a 16-bit destination offset.
- All conditional long branches require 4 bytes and 6 cycles if the branch is taken or 5 cycles if the branch is not taken.
- 5(6) means: 5 cycles if branch not taken, 6 cycles if taken.
Notes:
- This column gives a base cycle and byte count.
To obtain total count, add the values obtained from the INDEXED ADDRESSING MODE table, in Appendix F.
- R1 and R2 may be any pair of 8 bit or any pair of 16 bit registers.
The 8 bit registers are: A, B, CC, DP
The 16 bit registers are: X, Y, U, S, D, PC
- EA is the effective address.
- The PSH and PUL instructions require 5 cycles plus 1 cycle for each byte pushed or pulled.
- (moved up to Branch instructions)
- SWI sets I and F bits. SWI2 and SWI3 do not affect I and F.
- Conditions Codes set as a direct result of the instruction.
- Value of half-carry flag is undefined.
- Special Case - Carry set if b7 is SET.
© Motorola Inc., 1981 (now Freescale as of 2006)
Transformed into HTML by Matthias "Maddes" Bücher in 2006, 2007, 2023.
Use all information at your own risk.